Index: trunk/ippconfig/gpc1/crosstalk_rules.mdc =================================================================== --- trunk/ippconfig/gpc1/crosstalk_rules.mdc (revision 41553) +++ trunk/ippconfig/gpc1/crosstalk_rules.mdc (revision 41553) @@ -0,0 +1,5123 @@ +#TdB20210304: GPC1 crosstalk rules now set up in the recipes as a series of metadata blocks +CROSSTALK.RULE MULTI + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -8.91 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -9.83 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -9.30 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 40 + CROSS.MAGDIFF F32 -10.36 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 50 + CROSS.MAGDIFF F32 -10.00 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 60 + CROSS.MAGDIFF F32 -10.26 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 70 + CROSS.MAGDIFF F32 -9.83 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 0 + CHIP.OFFSET S32 20 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -9.54 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 0 + CHIP.OFFSET S32 20 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.35 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.02 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.99 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 0 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -9.46 +END + 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CHIP.OFFSET S32 10 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -10.76 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 0 + CHIP.OFFSET S32 10 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -10.28 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 1 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.97 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 1 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -10.03 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 1 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -10.31 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.38 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.77 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF 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CELL.SRC S32 2 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.57 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 2 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -10.59 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 2 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -10.48 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 2 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 40 + CROSS.MAGDIFF F32 -10.65 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 2 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 50 + CROSS.MAGDIFF F32 -10.23 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 3 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.37 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -10.38 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -10.05 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.96 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.60 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -10.51 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -10.39 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 40 + CROSS.MAGDIFF F32 -10.41 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 3 + CHIP.OFFSET S32 10 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -5.98 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -10.50 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -10.61 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -10.55 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.80 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.54 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -10.27 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -10.39 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 4 + CHIP.OFFSET S32 10 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.66 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 4 + CHIP.OFFSET S32 10 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -9.93 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 5 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -10.39 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -50 + CROSS.MAGDIFF F32 -10.48 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -10.54 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -10.68 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -10.42 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.90 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -6.83 +END + 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CROSS.MAGDIFF F32 -10.25 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -9.91 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -9.92 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -9.84 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -10.16 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 7 + CHIP.OFFSET S32 10 + CELL.OFFSET S32 -60 + CROSS.MAGDIFF F32 -10.18 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 2 + CELL.SRC S32 7 + CHIP.OFFSET S32 10 + CELL.OFFSET S32 -50 + CROSS.MAGDIFF F32 -7.71 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 0 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -9.47 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 0 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -8.59 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 0 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -9.87 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.32 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -9.76 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -9.21 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 40 + CROSS.MAGDIFF F32 -9.94 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 60 + CROSS.MAGDIFF F32 -10.05 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 1 + CHIP.OFFSET S32 -20 + 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CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.92 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.58 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -10.53 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 40 + CROSS.MAGDIFF F32 -10.52 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -10.16 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -10.30 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -9.76 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 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CROSS.MAGDIFF F32 -9.27 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -60 + CROSS.MAGDIFF F32 -9.52 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -50 + CROSS.MAGDIFF F32 -9.40 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -9.38 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -9.95 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -9.58 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 3 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.49 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.55 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -10.49 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -10.74 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 40 + CROSS.MAGDIFF F32 -10.82 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 50 + CROSS.MAGDIFF F32 -11.01 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 60 + CROSS.MAGDIFF F32 -10.65 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 70 + CROSS.MAGDIFF F32 -10.95 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 20 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -9.99 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 20 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.42 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 20 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -10.14 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 0 + CHIP.OFFSET S32 20 + CELL.OFFSET S32 70 + CROSS.MAGDIFF F32 -11.05 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.88 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -10.02 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -10.57 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -10.80 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 40 + CROSS.MAGDIFF F32 -10.65 +END + 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S32 0 + CELL.OFFSET S32 -60 + CROSS.MAGDIFF F32 -10.35 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -50 + CROSS.MAGDIFF F32 -10.30 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -10.29 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -10.29 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -10.38 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.85 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.86 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 6 + CHIP.OFFSET S32 20 + CELL.OFFSET S32 -60 + CROSS.MAGDIFF F32 -10.67 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CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -10.17 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -10.26 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -10.03 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -10.20 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 7 + CHIP.OFFSET S32 10 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.43 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 7 + CHIP.OFFSET S32 20 + CELL.OFFSET S32 -70 + CROSS.MAGDIFF F32 -10.70 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 4 + CELL.SRC S32 7 + CHIP.OFFSET S32 20 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -10.61 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 5 + CELL.SRC S32 0 + CHIP.OFFSET S32 -10 + CELL.OFFSET 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CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -10.30 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 5 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -10.58 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 5 + CELL.SRC S32 3 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 40 + CROSS.MAGDIFF F32 -10.33 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 5 + CELL.SRC S32 3 + CHIP.OFFSET S32 20 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.32 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 5 + CELL.SRC S32 4 + CHIP.OFFSET S32 -10 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.58 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 5 + CELL.SRC S32 4 + CHIP.OFFSET S32 -10 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -10.09 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 5 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -10.35 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 5 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF 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CROSS.MAGDIFF F32 -9.15 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 6 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.09 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 6 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.86 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 6 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -9.39 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 6 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -10.14 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 6 + CELL.SRC S32 1 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 60 + CROSS.MAGDIFF F32 -10.41 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 6 + CELL.SRC S32 2 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -10.27 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 6 + CELL.SRC S32 2 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -10.43 +END + +CROSSTALK.RULE METADATA + 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CROSS.MAGDIFF F32 -9.25 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -8.91 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -8.84 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -8.83 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -8.67 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 4 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 30 + CROSS.MAGDIFF F32 -8.97 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -8.94 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -9.39 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.29 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -9.11 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.39 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -9.48 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 -10 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -8.68 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -50 + CROSS.MAGDIFF F32 -9.02 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -9.13 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -9.16 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -8.86 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -8.35 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -8.78 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 5 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 20 + CROSS.MAGDIFF F32 -8.73 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -60 + CROSS.MAGDIFF F32 -10.19 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -50 + CROSS.MAGDIFF F32 -10.55 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -10.65 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -10.28 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.92 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -9.64 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -10.24 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 -10 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.45 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -60 + CROSS.MAGDIFF F32 -10.48 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -50 + CROSS.MAGDIFF F32 -10.38 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -9.35 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -9.08 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -9.78 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.23 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 6 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 10 + CROSS.MAGDIFF F32 -9.38 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 7 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -10.21 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 7 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -30 + CROSS.MAGDIFF F32 -10.41 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 7 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -9.95 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 7 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -10.05 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 7 + CHIP.OFFSET S32 -20 + CELL.OFFSET S32 0 + CROSS.MAGDIFF F32 -10.43 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -40 + CROSS.MAGDIFF F32 -9.23 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -20 + CROSS.MAGDIFF F32 -9.50 +END + +CROSSTALK.RULE METADATA + CHIP.SRC S32 7 + CELL.SRC S32 7 + CHIP.OFFSET S32 0 + CELL.OFFSET S32 -10 + CROSS.MAGDIFF F32 -9.08 +END + Index: trunk/ippconfig/gpc1/psastro.config =================================================================== --- trunk/ippconfig/gpc1/psastro.config (revision 41552) +++ trunk/ippconfig/gpc1/psastro.config (revision 41553) @@ -282,4 +282,7 @@ CROSSTALK_MAX_MAG F32 20.0 CROSSTALK_MASK BOOL TRUE + +# crosstal rules file is relative to PATH (eg, ippconfig directory) +CROSSTALK_FILE STR gpc1/crosstalk_rules.mdc PS1_REFERENCE METADATA