- Timestamp:
- May 4, 2011, 3:20:38 PM (15 years ago)
- Location:
- branches/czw_branch/20110406
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/czw_branch/20110406
- Property svn:mergeinfo changed
-
branches/czw_branch/20110406/ippconfig
- Property svn:mergeinfo changed (with no actual effect on merging)
-
branches/czw_branch/20110406/ippconfig/gpc1/format_20080929.config
r30878 r31434 666 666 XY76 STR 1111111111111111111111111111111111111111111111111111111111111111 667 667 END 668 668 PATTERN.CELL.SUBSET METADATA # List of chips and whether to do cell pattern correction 669 XY01 BOOL FALSE 670 XY02 BOOL FALSE 671 XY03 BOOL FALSE 672 XY04 BOOL FALSE 673 XY05 BOOL FALSE 674 XY06 BOOL FALSE 675 XY10 BOOL FALSE 676 XY11 BOOL FALSE 677 XY12 BOOL FALSE 678 XY13 BOOL FALSE 679 XY14 BOOL FALSE 680 XY15 BOOL FALSE 681 XY16 BOOL FALSE 682 XY17 BOOL FALSE 683 XY20 BOOL FALSE 684 XY21 BOOL FALSE 685 XY22 BOOL FALSE 686 XY23 BOOL FALSE 687 XY24 BOOL FALSE 688 XY25 BOOL FALSE 689 XY26 BOOL FALSE 690 XY27 BOOL FALSE 691 XY30 BOOL FALSE 692 XY31 BOOL FALSE 693 XY32 BOOL FALSE 694 XY33 BOOL FALSE 695 XY34 BOOL FALSE 696 XY35 BOOL FALSE 697 XY36 BOOL FALSE 698 XY37 BOOL FALSE 699 XY40 BOOL FALSE 700 XY41 BOOL FALSE 701 XY42 BOOL FALSE 702 XY43 BOOL FALSE 703 XY44 BOOL FALSE 704 XY45 BOOL FALSE 705 XY46 BOOL FALSE 706 XY47 BOOL FALSE 707 XY50 BOOL FALSE 708 XY51 BOOL FALSE 709 XY52 BOOL FALSE 710 XY53 BOOL FALSE 711 XY54 BOOL FALSE 712 XY55 BOOL FALSE 713 XY56 BOOL FALSE 714 XY57 BOOL FALSE 715 XY60 BOOL FALSE 716 XY61 BOOL FALSE 717 XY62 BOOL FALSE 718 XY63 BOOL FALSE 719 XY64 BOOL FALSE 720 XY65 BOOL FALSE 721 XY66 BOOL FALSE 722 XY67 BOOL FALSE 723 XY71 BOOL FALSE 724 XY72 BOOL FALSE 725 XY73 BOOL FALSE 726 XY74 BOOL FALSE 727 XY75 BOOL FALSE 728 XY76 BOOL FALSE 729 END 730
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